Title and Abstract

Title:  Hardware-software Codesign for Accelerating Data Science at the Edge

Abstract:  Data Science has matured over the past few years with novel applications in diverse areas including health, energy, autonomous x, etc. Many of these are cyber physical social systems with strict requirements of latency, throughput and energy efficiency. In many applications, the computations need to be performed at the “edge” as the data is collected. With recent dramatic advances in Field Programmable Gate Arrays (FPGAs), these devices are being used along with multi-core and novel memory technologies to realize advanced platforms to accelerate complex applications. This talk will review our recent work in the Data Science Lab at USC (dslab.usc.edu) and advances in reconfigurable computing (fpga.usc.edu) leading up to current trends in accelerators for data science. We will illustrate FPGA-based parallel architectures and algorithms for a variety of data analytics kernels in streaming graph processing and machine learning for “edge” processing. While demonstrating algorithm-architecture co-design methodology to realize high performance accelerators for graphs and machine learning, we demonstrate the role of modeling and algorithmic optimizations to develop highly efficient Intellectual Property (IP) cores. We show improved performance for two broad classes of graph analytics: iterative graph algorithms with variable workload (e. g., graph traversal, shortest paths, etc.) and machine learning on graphs (e. g., graph embedding). For variable workload iterative graph algorithms, we illustrate dynamic algorithm adaptation to exploit heterogeneity in the architecture. For graph embedding, we develop a novel computationally efficient technique using graph sampling and demonstrate scalable performance. We conclude by identifying opportunities and challenges in exploiting emerging heterogeneous architectures composed of multi-core processors, FPGAs, GPUs and coherent memory.